1. Field of the Invention
This invention relates to random access semiconductor memories particularly to a memory cell including both volatile and nonvolatile storage of information.
2. Description of the Prior Art
Volatile random access semiconductor memories have been built using bipolar and MOS transistors. Static semiconductor memories use flip-flops or cross-coupled inverters composed of bipolar or MOS transistors for each memory cell resulting in a memory that will hold the information in the memory cell so long as power supply voltages are maintained. The disadvantage of static memories is that each memory cell takes a lot of silicon area to fabricate resulting in large memory chips for a given memory size. In order to reduce the memory cell area, a simpler memory cell has been designed where the information is held in the memory cell by a charged capacitor which may be in the form of a capacitor or an expanded gate, source or drain electrode of a field effect transistor. The advantage of a simpler memory cell is that less silicon area is required per memory cell resulting in a smaller memory chip for a given number of storage bits. The disadvantage of using a capacitor to hold the information is that the charge stored on the capacitor tends to leak off through connecting circuit elements or through imperfect insulating barriers or their surfaces. Therefore, the capacitor holding the charge representing information needs to be periodically refreshed to restore the electrical charge on the capacitor as initially written. Memories utilizing a capacitor to hold the information may be referred to as dynamic memories to distinguish them from static memories. One example of a conventional dynamic memory cell utilizes a MOS transistor as a transmission gate to permit charge to be placed on a capacitor, a MOS transistor to be used as an inverter to sense the charge on the capacitor, and a MOS transistor used as a transmission gate to connect the output of the inverter to a data output line. The memory cell is periodically refreshed by the use of additional circuitry which periodically senses the information stored in the memory cell and rewrites the information back into the memory cell.
Both static and dynamic random access semiconductor memories have the disadvantage that when the circuit voltages are removed such as by turning off the power supply supplying the voltages to the memory cell, the information in the memory cell is lost. The information is lost because the voltages at key circuit nodes change with no assurance that when the power supply voltages are re-applied that the voltages will re-establish themselves as before. To prevent the loss of data from the memory cells in the event of loss of power supply voltages, a nonvolatile variable threshold transistor has been combined with the volatile memory cell which could store the information in nonvolatile form by a special write sequence which could be initiated at times the power supply voltages drop below a predetermined level. Information is not normally stored in the nonvolatile form due to the fact that the writing times are much longer than the times required to write the information in volatile form.
One example of a memory cell including volatile and nonvolatile storage of information is described in U.S. Pat. No. 3,761,901 issued on Sept. 25, 1973 to N. E. Aneshansley which utilizes two fixed threshold MOS transistors, a capacitor and a variable threshold field effect transistor. The variable threshold field effect transistor is used to hold nonvolatile information and at other times used to read or access volatile information from the memory cell. A major disadvantage of the memory cell such as shown in FIG. 2 is that when used in an array each row must be selected individually to write nonvolatile data. In addition, while the drain of the variable threshold field effect transistor is held at -18 volts, the gate may be at zero volts when its row is not selected and at -18 volts when selected. At the same time the drain may be at zero volts or at -18 volts depending upon the data stored on the gate of transistor 52. The voltages across the electrodes of the variable threshold field effect transistor may cause some read disturb effects to the preset condition or voltage threshold state of the variable threshold field effect transistor.
Another example of a memory cell which may store information in volatile and nonvolatile form is described in U.S. Pat. No. 3,774,177 issued on Nov. 20, 1973 to A. M. Schaffer. The memory cell is composed of two fixed threshold transistors, one variable threshold transistor and a capacitor. In Schaffer the variable threshold transistor is used as a transmission gate to place charge on the capacitor and to store the nonvolatile information at times when a write pulse is applied to its gate. With the memory cells arranged in an array such as shown in FIG. 3, it has a disadvantage in that only one row of memory cells may be written into at a time to store nonvolatile information. In addition, various voltages are placed across the gate, drain and source electrodes of the variable threshold field effect transistor during the operation of read and write of volatile and nonvolatile information.
Another memory circuit for storing volatile and nonvolatile information is described in U.S. Pat. No. 3,922,650 issued on Nov. 25, 1975 to A. M. Shaffer which describes a random access memory cell comprised of three capacitors, two fixed threshold field effect transistors and one variable threshold field effect transistor. One of the capacitor's capacitance varies as a function of the data and is used to read information out of another capacitor. The variable threshold transistor is also used to write data into the memory cell in volatile form, to refresh the (volatile) charge on a capacitor and to hold nonvolatile data by placing a negative write pulse on the gate. The disadvantage of the memory cell is that various voltages are placed across the gate and drain and source electrodes of the variable threshold transistor during operation of the memory cell.
It is therefore desirable to have a memory cell capable of storing volatile and nonvolatile information which does not depend upon the variable threshold transistor during reading or writing of volatile information.
It is further desirable that the variable threshold transistor be placed in the memory cell circuit at a point where voltages during operation of the memory for storing or reading volatile information does not cause excessive voltages to appear across the electrodes of the variable threshold transistor resulting in voltage threshold shifts or effects to the gate insulator.
It is further desirable that in an array of memory cells that the entire array may be written with nonvolatile information at one time.
It is further desirable that an entire array of memory cells may be cleared of the nonvolatile information at one time.
It is further desirable that the memory cell contain as few components as possible and require the least silicon area for its implementation to permit memory chips to contain many memory cells.